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Description: Discussing Verilog and PLI.
 

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By DG shoes wholeslaer  - 5:18am - 1 new of 1 message    

how to I test putting in a value of "X" and "Z" on a reg in testbench code? 
  ...sorry I don't have the software on my machine yet so I can't test this, but need to know the syntax for this. i.e. do I just say myreg = X; ??
By andersod2  - Sep 2 - 6 new of 6 messages    

mux with inputs of "X" or "Z"...? 
  What happens if I have a module that is a simple 1-bit mux, where the select line selects A or B, and A is "X", and B is "Z"...? (And let's say the select line is set to "B")...does this mean the output will just be "Z" or is there some kind of error condition associated with this? Under what circumstances would something like this happen (i.e.... more »
By andersod2  - Sep 2 - 10 new of 10 messages    

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By hghg  - Aug 29 - 1 new of 1 message    

Yes we have Gravity but why? 
  Yes we have Gravity but why? A correct theory of gravity will show us these four (4) things ...1. It will show us why gravity also acts like acceleration (principle of equvalence). 2. It will show us the actual cause of gravity. 3. It will show us why gravitational mass and inertial mass are identical.... more »
By fitz  - Aug 29 - 1 new of 1 message    

Using SV DPI-C to model with OpenCV or DPI-C and pointers and data-structures 
  Hi, In trying to create an image processing modeling environment, I decided to leverage the DPI-C and OpenCV. One of the key aspects of OpenCV is to be able to pass around a pointer (IplImage*) to a data- structure that holds and describes an image. I am wondering if there is a way for me to directly call the routines that create and... more »
By fpgabuilder  - Aug 27 - 5 new of 5 messages    

carry look-ahead adder 
  i connected 2 4-bit carry look-ahead adders. everything worked fine but i dont see COUT2 in my simulation window.. whats the problem ?? // 1st cla module alu1(cout,sum,x,y,cin); output cout; output [3:0] sum; input [3:0] x,y; input cin; wire [3:0] g,p; wire [4:0] c; assign c[0] = cin; assign g[3:0] = x[3:0] & y[3:0];... more »
By khushalgelda  - Aug 26 - 3 new of 3 messages    

Display with alignment 
  Hi All, I need some help in displaying decimal numbers with alignment to get the output below: [001000] TEST01: 1 TEST02: 1 TEST03: 0 NUMBER [002000] TEST01: 10 TEST02: 5 TEST03: 1 NUMBER [003000] TEST01: 150 TEST02: 25 TEST03: 10 NUMBER [004000] TEST01: 15 TEST02: 2 TEST03: 10 NUMBER I tried the below code:... more »
By Deepu  - Aug 25 - 6 new of 6 messages    

SV programs - Re: Does Modelsim ASE support SystemVerilog? 
  ...Please elaborate!
By David Rogoff  - Aug 20 - 4 new of 4 messages    

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