Description:
Discussing Verilog and PLI.
|
|
|
1800-2009 and $fatal
|
| |
There appears to be an inconsistency in 1800-2009. In 20.9 it says that the first argument to $fatal shall be consistent with the first argument to $finish, namely, an integer 0, 1, or 2 (as defined in 20.2). However, the examples on pages 315 and 405 use '$fatal("Sorry");' Is the first argument to $fatal optional, or is the example code buggy?... more »
|
|
|
Why doesn't this situation generate a latch?
|
| |
Hi, I have a question about when to generate a latch. In Example_1 and Exmaple_2, I don't think it will generate a latch. I don't know why. Example_1: process(RESET, CLK) Begin If RESET = 1 then StateA <= S0; Elsif CLKevent = 1 and CLK = 1 then If SINI = 1 then StateA <= S0;... more »
|
|
|
SystemVerilog queue initialization using ncverilog +sv?
|
| |
I have a question for the assembled masses. I have a declaration similar to the following: integer my_q[$] = {1,2,3,4,5,6}; This is accepted by Modelsim using the -sv switch. If I compile this with ncverilog +sv I get the following gripes: ncvlog: *E,TYCMPAT (queue.sv,5|18): assignment operator type check... more »
|
|
|
weird simulation problems for a PC module
|
| |
my code is the following: module PC(in, Clk, out); input Clk; input[31:0] in; output[31:0] out; reg[31:0] out; reg[31:0] PC; initial PC <= 32'b00000000000000000000000000 00000; always @(posedge Clk) begin PC <= in; out <= PC; end endmodule it is just a code for a program counter, I've set the initial value of... more »
|
|
|
shift right arithmetic
|
| |
is there an equivalent way in verilog to do this: The contents of the low-order 32-bit word of a number are shifted right, duplicating the sign-bit (bit 31) in the emptied bits
|
|
|
What is the difference between St0 and 0? (Modelsim)
|
| |
Likewise for St1 and 1. I've searched the documentation for Modelsim inside out and can't find any good reason why it writes the vale "0" for some nets in my waveform and "St0" for others. I assume that St0 means strong0 and St1 means strong1. The manual says that 0 and 1 correspond to strong0 and strong1, so why doesn't it just use 0 and 1?... more »
|
|
|
renaming a source file
|
| |
This might be a super noob question to post here. I am using xilinx ise as my verilog IDE. Say I have a source file called test.v and I want to rename this to something else.. is there a way to do this?
|
|
|
Is an inout reg allowed
|
| |
I've tried to use an inout reg with quartus and it doesn't give a warning. However, I read on the internet that an inout port can only be a wire. Which one is true?
|
|
|
SV interface in modules instantiated inside a generate statement
|
| |
How do I replace the i/os on the modules repeatedly instantiated as below with an instance of an interface? module top_level #(parameter NUM_OF_ADC_INTERFACES=`ADC_BRD _FPGA_NUM_OF_ADC_INTERFACES, NUM_OF_CHANNELS_PER_ADC_INTERF ACE=`ADC_BRD_FPGA_NUM_OF_CHANN ELS_PER_ADC_INTERFACE ) ( //adc channel interfaces... more »
|
|
|
single cycle datapath
|
| |
I am not sure if this is the right place to ask but since I am implementing this in verilog then I'll go ask. I am implementing a single cycle datapath to support for the MIPS instruction architecture. A few of the instructions I will be doing is mfhi, mflo, mthi, mtlo. And also several loads/stores, such as lw, sw, lh, sh, sb, lb.... more »
|
|
|
|
